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| i2Chip W3100A www.i2Chip.com Technical Datasheet v1.1 Description G The i2Chip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution Features 6/Hardware Internet protocols included: TCP, IP Ver.4, UDP, ICMP, ARP 6/Hardware Ethernet protocols included: DLC, MAC 6/Supports 4 independent connections simultaneously 6/Internal ICMP responds to PING commands 6/Protocol processing speed: full-duplex 4~5 Mbps 6/Intel/Motorola MCU bus Interface 6/I C Interface 6/Standard MII Interface for under-layer physical chip 6/Socket API support for easy application programming 6/Supports full-duplex mode 6/Internal 16Kbytes Dual-port SRAM for data buffer 6/0.35 m CMOS technology 6/Wide operating voltage: 3.3V internal operation, 5V tolerant 3.3V IOs 6/Small 64 Pin LQFP Package 2 Description for high-speed Internet connectivity for digital devices Features by allowing simple installation of TCP/IP stack in the Block Diagram hardware. G The W3100A offers system designers a quick, Implementing this LSI into a system easy way to add Ethernet networking functionality to any product. can completely offload Internet connectivity and processing standard protocols from the system, thereby significantly reducing the software development cost. The W3100A contains TCP/IP Protocol Stacks such as TCP, UDP, IP, ARP and ICMP protocols, as well as Ethernet protocols such as Data Link Control and MAC protocol. The W3100A offers a socket API (Application Programming Interface) that is similar to the windows socket API. The chip offers Intel and Motorola 2 Block Diagram MODE0 MODE1 MODE2 MCU (8051, i386, 6811 tested) bus interface and I C for upper-layer and supports standard MII interface for under-layer Ethernet. The W3100A can be applied to handheld devices including Internet phones, VoIP SOC chips, Internet MP3 players, handheld medical devices, LAN cards for Web servers, cellular phones and many other nonportable electronic devices such as large consumer electronic products.G Protocol Engine ICMP TCP UDP MCU Interface IP DLC MAC ARP SCL SDA CLOCK EXT_CLK RESET MII Interface RX_CLK RXDV/CRS RXD(3:0) TX_CLK TXE TXD(3:0) COL /SERIAL /FDPLX /LINK ~pGGyhwpkGOyGhTGpGwGkPH/ : DPRAM /CS /WR /RD /INT ADDR(14:0) DATA(7:0) Table of Contents G G G G G G G k UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG mUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG iGk UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XG wGhUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ZG zGk UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [G yGkUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XXG XUGjGy UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU XXG YUGzGyUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU X]G ZUGwGyUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU X_G [UGjGy UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YWG G G pGtGGy UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU YZG kGGmUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Y\G XUGpGG~ZXWWhUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Y\G YUG{jwGw UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Y\G ZUG|kwGw UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ZYG [UGpwGsGyh~GtUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Z\G \UGthjGsGyh~Gt UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Z]G G hGpUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [WG XUGyGGtj|GiGpVmGtGGtGGOtYaWP UUUUUUUUUUUUUUUUUUUUUUUUUUUU [WG YUGkGiGpVmGtU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [XG ZUGpGiGpVmGtU UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [XG [UGp jGpVmGtUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [ZG \UGwGsGpUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU [_G G {Gk UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \WG XUGjGOjsvjrGdGY\toP UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \WG YUGlGGOl{jsrGdG\WtoP UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \YG ZUGuTGOjsvjrGdGY\toP UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \[G [UGp jGOjsvjrGdGY\toPUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \^G \UGtGpGpGOtppP UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU \G G G G G wGk UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ]XG hGhUG G lGzUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU ]YG ; ; ~pGGyhwpkGOyGhTGpGwGkPHG Y Pin Assignment G Figure 1: 64-Pin LQFP Pin Assignments TX_CLK MODE0 TXD[3] TXD[2] TXD[1] 50 64 RESET VCC GND CLOCK A[14]/DA[6] A[13]/DA[5] A[12]/DA[4] A[11]/DA[3] A[10]/DA[2] A[9]/DA[1] A[8]/DA[0] VCC GND A[7] A[6] A[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A[4] 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 47 46 45 44 43 42 41 COL MODE1 RX_CLK GND RXDV/CRS RXD[3] RXD[2] RXD[1] RXD[0] VCC VCC GND /LINK /SERIAL /FDPLX EXT_CLK TXD[0] 40 39 38 37 36 35 34 33 32 D[0] GND GND 27 D[4] VCC SDA i2Chip W3100A 64-LQFP 18 A[3] 19 A[2] 20 A[1] 21 A[0] 22 VCC 23 GND 24 D[7] 25 D[6] 26 D[5] 28 MODE2 TXE /WR SCL /INT /RD /CS 29 D[3] 30 D[2] 31 D[1] G G ~pGGyhwpkGOyGhTGpGwGkPHG Z Signal Description Table 1: W3100A MII Signal Description PIN# 52 51 50 49 53 Signal TXD[3] TXD[2] TXD[1] TXD[0] TXE I/O O Description TRANSMIT DATA: Nibble/Serial NRZ data output to the ENDEC that is valid on the rising edge of TX_CLK. In serial mode, the TXD[0] pin is used as the serial data pin, and TXD[3:1] are ignored. O TRANSMIT ENABLE: becomes active when the first nibble/serial data of the packet is valid on TXD[3:0] and goes low after the last nibble/serial data of the packet is clocked out of TXD[3:0]. signal connects directly to the ENDEC (PHY device). is active high. This This signal 55 TX_CLK I TRANSMIT CLOCK: TX_CLK is sourced by the PHY. TX_CLK is 2.5 MHz in 10BASE-T Nibble mode, and 25 MHz in 100BASE-T Nibble mode. 43 42 41 40 44 RXD[3] RXD[2] RXD[1] RXD[0] RXDV/CRS I RECEIVE DATA: Nibble wide receive data (synchronous to RX_CLK) that must be driven on the falling edge of RX_CLK. In serial mode, the RXD[0] pin is used as the data input pin which is also clocked in on the falling edge of RX_CLK. and become don't cares. RXD[3:1] pins I CARRIER SENSE: signal provided by the ENDEC and indicates that carrier is present. This signal is active high. 46 48 RX_CLK COL I I RECEIVE CLOCK: Re-synchronized clock from the ENDEC and indicates that carrier is present. COLLISION DETECT: becomes active when a collision has been detected in Half Duplex modes. This signal is asynchronous, active high and ignored during fullduplex operation. Table 2: W3100A MCU Interface Signal Description PIN# 5-11 Signal A[14-8] / DA[6-0] I/O I Description ADDRESS PINS / DEVICE ADDRESS PINS Used as Address[14 - 8] pin when set in MCU Bus Interface mode. Used as Device address[6 - 0] pin for I C Interface when set in 2 I C Interface mode. 14-21 24-27 29-32 61 A[7-0] D[7-4] D[3-0] /INT O INTERRUPT: Indicates that the W3100A requires MCU attention after reception or transmission. The interrupt is cleared by writing to the ISR (Interrupt Status Register). 64 /CS I All interrupts are maskable by writing IMG (Interrupt Mask Register). This signal is active low. CHIP SELECT: This signal is active low. I I/O ADDRESS PINS DATA PINS 2 ~pGGyhwpkGOyGhTGpGwGkPHG [ 62 63 59 60 /WR /RD SCL SDA I I I I/O WRITE ENABLE: This signal is active low. READ ENABLE: This signal is active low. SCL: clock used by I C when using I C Interface mode External Pull high (4.7 k) is required. SDA: data used by I C when using I C Interface mode External Pull high (4.7 k) is required. 2 2 2 2 Table 3: W3100A Miscellaneous Signal Description PIN# 1 Signal RESET I/O I Description RESET: Active High input that initializes or reinitializes the W3100A. Asserting this pin will force a reset process to occur which will result in all internal registers reinitializing to their default states as specified for each bit in section x.x, and all strapping options are reinitialized. Refer to section x.x for further detail regarding reset. 4 CLOCK I CLOCK: primary clock required for internal operation of W3100A. In general, PHY driving clock is shared for saving cost. (25MHz is recommended) Note) Sharing crystal source clock with multiple devices may cause some troubles. In our reference design, we used Realtek's PHY and one crystal for both PHY and W3100A with verification. But for other kind of PHY, please confirm safety prior to decision. 33 EXT_CLK I EXTERNAL CLOCK: supplementary clock used for MCU I/F of W3100A. In external clocked mode, W3100A uses this clock to interface with MCU, and the access time of W3100A varies upon the frequency of the external clock. Refer to xx for detailed timing diagram. Frequency higher than 25MHz clock rate is granted. 36 /LINK I LINK: This is the signal generated by Ethernet PHY to indicate the PHY is connected to the Ethernet HUB device or other peer device. This is active low. W3100A can knows the status of physical line connection with this /LINK input. If /LINK is high, W3100A interprets the physical line is disconnected. It results in TCP timeout and connection close. In special PHY case, LINK signal varies in time, which can be grounded. 35 /SERIAL I 10BASE-T SERIAL/NIBBLE SELECT: With the selection of this active low input, transmit and receive data are exchanged serially at a 10 MHz clock rate on the least significant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0], respectively. This mode is intended for use with the W3100A connected to a PHY using a 10 Mb/s serial interface. There is an internal pull-up resister for this pin. If this pin is left floated externally, then the device will be configured to normal mode. This pin must be externally pulled low (typically x k) in ~pGGyhwpkGOyGhTGpGwGkPHG \ order to configure the W3100A for Serial MII operation. 34 /FDPLX I FULL/HALF DUPLEX SELECT: This input pin selects Half/Full Duplex operation. This pin must be externally pulled low (typically x k) in order to configure the W3100A for Full Duplex operation. 0 = Full Duplex 1 = Half Duplex 28, 47, 56 MODE[2- 0] I MODE SELECT: This input pin selects MCU I/F type and operating mode of W3100A. Since each pin is positioned as pull-down internally, clock mode - the default mode - is selected when the connection is not made. M2 0 M1 0 M0 0 Clocked mode Description Mode where MCU Bus signal is analyzed by W3100A by using the clock when MCU Bus I/F is in use. 0 0 1 External clocked mode 0 1 0 Nonclocked mode 0 1 1 X 1 X Mode where MCU Bus signal is analyzed by W3100A by using the external clock when MCU Bus I/F is in use. Mode where MCU bus signal is used directly by W3100A when MCU Bus I/F is in use. Mode using I C for MCU I/F. Mode used for testing at the plant. Not to be used by regular users. 2 IC mode Test mode 2 Clocked mode, External clocked mode and Non-clocked mode are used to connect MCU and W3100A when MCU Bus I/F is in use. Choose an appropriate mode and use it by analyzing the MCU bus timing. Refer to timing diagram for each mode for more detail. Table 4: W3100A Power Supply Signal Description PIN# 2, 12, 22, 38, 39, 58 3, 13, 23, 37, 45, 54, 57 GND NEGATIVE (GROUND) SUPPLY PINS: a decoupling capacitor is recommended to be connected between the Vcc and GND pins Signal VCC I/O Description POSITIVE 3.3V SUPPLY PINS ~pGGyhwpkGOyGhTGpGwGkPHG ] Table5. W3100A Registers Map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A - 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 - 0x13 0x14 - 0x17 0x18 - 0x1B 0x1C - 0x1F 0x20 - 0x23 0x24 - 0x27 Register C0_CR C1_CR C2_CR C3_CR C0_ISR C1_ISR C2_ISR C3_ISR IR IMR Reserved IDM_OR IDM_AR0 IDM_AR1 IDM_DR C0_RW_PR C0_RR_PR C0_TA_PR C1_RW_PR C1_RR_PR C1_TA_PR IND_EN Indirect bus I/F mode Address0 Register Indirect bus I/F mode Address1 Register Indirect bus I/F mode Data Register Channel 0 Rx Write Pointer Register Channel 0 Rx Read Pointer Register Channel 0 Tx ACK Pointer Register Channel 1 Rx Write Pointer Register Channel 1 Rx Read Pointer Register Channel 1 Tx ACK Pointer Register L/B AUTO_INC C3R IM_C3R S/W Reset Memory Test Recv Recv Recv Recv Recv_OK Recv_OK Recv_OK Recv_OK C2R IM_C2R Send Send Send Send Send_OK Send_OK Send_OK Send_OK C1R IM_C1R Bit Definitions Close Close Close Close Timeout Timeout Timeout Timeout C0R IM_C0R Listen Listen Listen Listen Closed Closed Closed Closed C3 IM_C3 Connect Connect Connect Connect Established Established Established Established C2 IM_C2 Sock_Init Sock_Init Sock_Init Sock_Init SInit_OK SInit_OK SInit_OK SInit_OK C1 IM_C1 C0 IM_C0 Init_OK Sys_Init oGpGjG~GO~pSGpUPG ^G 0x28 - 0x2B 0x2C - 0x2F 0x30 - 0x33 0x34 - 0x37 0x38 - 0x3B 0x3C - 0x3F 0x40 - 0x43 0x44 - 0x47 0x48 - 0x4B 0x4C - 0x4F 0x50 - 0x53 0x54 - 0x57 0x58 - 0x5B 0x5C - 0x5F 0x60 - 0x63 0x64 - 0x67 0x68 - 0x6B 0x6C - 0x7F 0x80 - 0x83 0x84 - 0x87 0x88 - 0x8D 0x8E - 0x91 0x92 - 0x93 C2_RW_PR C2_RR_PR C2_TA_PR C3_RW_PR C3_RR_PR C3_TA_PR C0_TW_PR C0_TR_PR Reserved C1_TW_PR C1_TR_PR Reserved C2_TW_PR C2_TR_PR Reserved C3_TW_PR C3_TR_PR Reserved GAR SMR SHAR SIPR IRTR Channel 2 Rx Write Pointer Register Channel 2 Rx Read Pointer Register Channel 2 Tx ACK Pointer Register Channel 3 Rx Write Pointer Register Channel 3 Rx Read Pointer Register Channel 3 Tx ACK Pointer Register Channel 0 Tx Write Pointer Register Channel 0 Tx Read Pointer Register Channel 1 Tx Write Pointer Register Channel 1 Tx Read Pointer Register Channel 2 Tx Write Pointer Register Channel 2 Tx Read Pointer Register Channel 3 Tx Write Pointer Register Channel 3 Tx Read Pointer Register Gateway Address Register Subnet Mask Register Source Hardware Address Register Source IP Address Register Initial Retry Time-value Register oGpGjG~GO~pSGpUPG _G 0x94 0x95 0x96 0x97 - 0x9F 0xA0 0xA1 0xA2 - 0xA7 0xA8 - 0xAB 0xAC - 0xAD 0xAE - 0xAF 0xB0 0xB1 0xB2 - 0xB3 0xB4 - 0xB7 0xB8 0xB9 0xBA - 0xBF 0xC0 - 0xC3 0xC4 - 0xC5 0xC6 - 0xC7 0xC8 0xC9 0xCA - 0xCB RCR RMSR TMSR Reserved C0_SSR C0_SOPR Reserved C0_DIR C0_DPR C0_SPR C0_IPR C0_TOSR C0_MSSR Reserved C1_SSR C1_SOPR Reserved C1_DIR C1_DPR C1_SPR C1_IPR C1_TOSR C1_MSSR Channel 1 Destination IP Address Register Channel 1 Destination Port Register Channel 1 Source Port Register Channel 1 IP Protocol Register Channel 1 TOS (type of service) Register Channel 1 MSS (maximum segment size) Register Channel 1 Socket Status Register Broadcast NDTimeout NDAck Channel 0 Destination IP Address Register Channel 0 Destination Port Register Channel 0 Source Port Register Channel 0 IP Protocol Register Channel 0 TOS (type of service) Register Channel 0 MSS (maximum segment size) Register Channel 0 Socket Status Register Broadcast/ERR NDTimeout/B NDAck Rx data Memory Size Register Tx data Memory Size Register TC4 TC3 TC2 TC1 TC0 SWS/P Protocol Protocol Protocol SWS Protocol Protocol Protocol oGpGjG~GO~pSGpUPG G 0xCC - 0xCF 0xD0 0xD1 0xD2 - 0xD7 0xD8 - 0xDB 0xDC 0xDD 0xDE - 0xDF 0xE0 0xE1 0xE2 - 0xE3 0xE4 - 0xE7 0xE8 0xE9 0xEA - 0xEF 0xF0 - 0xF3 0xF4 - 0xF5 0xF6 - 0xF7 0xF8 0xF9 0xFA - 0xFB 0xFC - 0xFF - Reserved C2_SSR C2_SOPR Reserved C2_DIR C2_DPR Channel 2 Destination IP Address Register Channel 2 Destination Port Register Channel 2 Socket Status Register Broadcast NDTimeout NDAck SWS Protocol Protocol Protocol C2_SPR C2_IPR C2_TOSR C2_MSSR Reserved C3_SSR C3_SOPR Reserved C3_DIR C3_DPR C3_SPR C3_IPR C3_TOSR C3_MSSR Reserved Channel 2 Source Port Register Channel 2 IP Protocol Register Channel 2 TOS (type of service) Register Channel 2 MSS (maximum segment size) Register Channel 3 Socket Status Register Broadcast NDTimeout NDAck SWS Protocol Protocol Protocol Channel 3 Destination IP Address Register Channel 3 Destination Port Register Channel 3 Source Port Register Channel 3 IP Protocol Register Channel 3 TOS (type of service) Register Channel 3 MSS (maximum segment size) Register oGpGjG~GO~pSGpUPG XWG Register Definitions. Register sets are categorized into (i) control registers related to command, status and interrupt, (ii) system registers for gateway address, subnet mask, source IP, source HA (Hardware Address) and timeout value, (iii) pointer registers for managing to send, receive data, and (iv) channel registers that control operation of each channel. allowed. R/W access to reserved register is not allowed, and also, writing on read-only register is not 1. Control Registers C0_CR (Channel 0 Command Register) [R/W, 0x00] This register commands Channel 0 socket to initialize, connect, close, transmit and receive data. Sys_Init command is used to set the gateway, subnet mask, source IP and source H/W Address. The same command is used to close the socket in all channels. Sock_Init, Connect, Listen, Close, Send and Recv are used when initializing, establishing a connection, terminating a connection, sending and receiving data for Channel 0 socket. automatically cleared after executing the command. Sock_Init command opens the corresponding Channel in TCP, UDP, RAW mode according to the protocol value as set at C0_SOPR (Channel 0 Socket Option Protocol Register). MCU can initialize the internal setting value of the chip by using S/W Reset. Each bit in this register is automatically cleared after executing the command. Each corresponding bit is 7 S/W Reset 6 Recv 5 Send 4 Close 3 Listen 2 Connect 1 Sock_Init 0 Sys_Init Bit D0 Symbol Sys_Init Description Command to set Gateway IP Address, Subnet Mask, Source H/W Address, Source IP Address D1 Sock_Init Command to set corresponding protocol at C0_SOPR and open Channel 0 socket D2 D3 Connect Listen Command for Channel 0 socket to make a connection to the server Command to stand by for connection when Channel 0 socket acts in server mode D4 D5 D6 D7 Close Send Recv S/W Reset Command to terminate connection and close Channel 0 socket Command to transmit Channel 0 socket data Command to receive Channel 0 socket data S/W Reset command oGpGjG~GO~pSGpUPG XX C1_CR (Channel 1 Command Register) [R/W, 0x01] This register commands Channel 1 Socket to initialize, connect, close, transmit and receive data. Sock_Init, Connect, Listen, Close, Send and Recv are used when initializing, establishing a connection, terminating a connection, sending and receiving data for Channel 1 socket. automatically cleared after executing the command. Memory test command is used to verify transmission and reception memory where MCU reads and writes for the transmission and reception memory. Set memory test bit to `1' to become toggled as `0', `1' and Memory test bit needs to become set at `0' in order for Each corresponding bit is W3100A acts in memory test mode when in `1'. W3100A to execute normal data transmission and reception. 7 Memory Test 6 Recv 5 Send 4 Close 3 Listen 2 Connect 1 Sock_Init 0 Bit D0 D1 D2 Symbol Reserved Sock_Init Connect Description Sets corresponding protocol at C1_SOPR and opens Channel 1 socket Command for Channel 1 socket to act in client mode to make a connection to the server D3 Listen Command to stand by for connection when Channel 1 socket acts in server mode D4 D5 D6 D7 Close Send Recv Memory Test Command to terminate connection and close Channel 1 socket Command to transmit Channel 1 socket data Command to receive Channel 1 socket data Command to set memory test mode C2_CR, C3_CR (Channel 2, 3 Command Register) [R/W, 0x02, 0x03] This register commands each Channel 2, 3 sockets to initialize, connect, close, transmit and receive data. Sock_Init, Connect, Listen, Close, Send and Recv are used when initializing, establishing a connection, terminating a connection, sending and receiving data for corresponding socket. automatically cleared after executing the command. Each corresponding bit is 7 6 Recv 5 Send 4 Close 3 Listen 2 Connect 1 Sock_Init 0 Bit D0 Symbol Reserved Description oGpGjG~GO~pSGpUPG XY D1 Sock_Init Sets corresponding protocol at Cx_SOPR and opens corresponding channel socket D2 Connect Command for corresponding channel socket to act in client mode to make a connection to the server D3 Listen Command to stand by for connection when corresponding channel socket acts in server mode D4 D5 D6 D7 Close Send Recv Command to terminate connection and close corresponding channel socket Command to transmit corresponding channel socket data Command to receive corresponding channel socket data Reserved C0_ISR (Channel 0 Interrupt Status Register) [R, 0x04] This register notifies the outcome of Channel 0 socket command. This register becomes cleared as 0x00 by read operation. Init_OK notifies the completion of Sys_Init command. Established notifies the completion of a connection executed by connection set-up command (Connect, Listen). Timeout notifies an occurrence of a time out while executing connection set-up command (Connect, Listen) or Send command. SInit_OK, Closed, Send_OK and Recv_OK each notifies the completion of Sock_Init, Close, Send and Recv commands, respectively. 7 6 Recv_OK 5 Send_OK 4 Timeout 3 Closed 2 Established 1 SInit_OK 0 Init_OK Bit D0 D1 D2 D3 D4 Symbol Init_OK SInit_OK Established Closed Timeout Description Interrupt status bit for completion of Sys_Init command Interrupt status bit for completion of Channel 0 socket Sock_Init command Interrupt status bit for completion of Channel 0 socket connection set-up Interrupt status bit for completion of Channel 0 socket connection ending Interrupt status bit for occurrence of time out during Channel 0 socket connection set-up or data transmission D5 D6 D7 Send_OK Recv_OK Interrupt status bit for completion of Channel 0 socket Send command Interrupt status bit for completion of Channel 0 socket Recv command Reserved oGpGjG~GO~pSGpUPG XZ C1_ISR, C2_ISR, C3_ISR (Channel 1, 2, 3 Interrupt Status Register) [R, 0x05, 0x06, 0x07] This register notifies the outcome of the command of each Channel 1, 2 and 3. This register becomes cleared as 0x00 by read operation. Established notifies the completion of a connection executed by connection set-up command (Connect, Listen). Timeout notifies an occurrence of a time out while executing connection set-up command (Connect, Listen) or Send command. SInit_OK, Closed, Send_OK and Recv_OK each notifies the completion of Sock_Init, Close, Send and Recv commands, respectively. 7 6 Recv_OK 5 Send_OK 4 Timeout 3 Closed 2 Established 1 SInit_OK 0 Bit D0 D1 Symbol Reserved SInit_OK Description Interrupt status bit for completion of corresponding channel socket Sock_Init command D2 Established Interrupt status bit for completion of corresponding channel socket connection set-up D3 Closed Interrupt status bit for completion of corresponding channel socket connection ending D4 Timeout Interrupt status bit for occurrence of time out during corresponding channel socket connection set-up or data transmission D5 Send_OK Interrupt status bit for completion of corresponding channel socket Send command D6 Recv_OK Interrupt status bit for completion of corresponding channel socket Recv command D7 Reserved IR (Interrupt Register) [R/W, 0x08] This register is used to sort channel with occurring interrupt. C0, C1, C2 and C3 bit notify each of 0, 1, 2 and 3 channels that an interrupt has occurred. MCU can identify which interrupt has occurred by examining the Channel Interrupt Status Register of the corresponding channel. C0R, C1R, C2R and C3R Bit notify that data transmission has occurred for 0, 1, 2 and 3 Channel. This register can clear the interrupt signal by writing `1' at the corresponding bit. oGpGjG~GO~pSGpUPG X[ 7 C3R 6 C2R 5 C1R 4 C0R 3 C3 2 C2 1 C1 0 C0 Bit D0 D1 D2 D3 D4 D5 D6 D7 Symbol C0 C1 C2 C3 C0R C1R C2R C3R Description Occurrence of Channel 0 Socket Interrupt Occurrence of Channel 1 Socket Interrupt Occurrence of Channel 2 Socket Interrupt Occurrence of Channel 3 Socket Interrupt Occurrence of Channel 0 Socket data receipt Occurrence of Channel 1 Socket data receipt Occurrence of Channel 2 Socket data receipt Occurrence of Channel 3 Socket data receipt IMR (Interrupt Mask Register) [R/W, 0x09] This register is used to mask an interrupt from each bit of the corresponding interrupt register. Interrupt is enabled when the corresponding bit of the interrupt register is set by setting the corresponding bit at `1'. 7 IM_C3R 6 IM_C2R 5 IM_C1R 4 IM_C0R 3 IM_C3 2 IM_C2 1 IM_C1 0 IM_C0 Bit D0 D1 D2 D3 D4 D5 D6 D7 Symbol IM_C0 IM_C1 IM_C2 IM_C3 IM_C0R IM_C1R IM_C2R IM_C3R Description Channel 0 Socket Interrupt Enable. Channel 1 Socket Interrupt Enable. Channel 2 Socket Interrupt Enable. Channel 3 Socket Interrupt Enable. Channel 0 Socket data receipt Interrupt Enable. Channel 1 Socket data receipt Interrupt Enable. Channel 2 Socket data receipt Interrupt Enable. Channel 3 Socket data receipt Interrupt Enable. IDM_OR (InDirect Mode Option Register) [R/W, 0x0C] This register facilitates indirect bus I/F mode enable and option set-up. IND_EN (indirect mode enable) bit enables indirect bus I/F mode. indirect bus I/F mode to another I/F. L/B (Little-endian/Big-endian) bit enables the access to indirect address register as Little-endian (`1') or Bigendian (`0'). H/W reset is required to convert from oGpGjG~GO~pSGpUPG X\ AUTO_INC (auto-increment) bit automatically increases the address during an access to indirect data register. 7 IND_EN 6 5 4 3 2 1 L/B 0 AUTO_INC Bit D7 D6 D5 D4 D3 D2 D1 D0 Symbol IND_EN Indirect bus I/F mode Enable. Reserved Reserved Reserved Reserved Reserved L/B AUTO_INC Description Little-endian/Big-endian ordering setting register. Address auto-increment Enable IDM_AR0, IDM_AR1 (InDirect Mode Address Register) [R/W, 0x0D - 0x0E] This register is for address set-up when indirect bus I/F mode is in use, and the ordering changes according to the L/B bit set-up of IM_OPT register. When L/B bit of IDM_OPT register = `0' MSB IDM_ADDR0(0x0D) When L/B bit of IDM_OPT register = `1' LSB IDM_ADDR0(0x0D) MSB IDM_ADDR1(0x0E) IDM_ADDR1(0x0E) LSB IDM_DR (Indirect Mode Data Register) [R/W, 0x0F] This register is for data when indirect bus I/F mode is in use. 2. System Registers GAR (Gateway Address Register) [R/W, 0x80 - 0x83] This register sets up the default gateway address to be used in the system, which is required to be set IP address before executing Sys_Init command. SMR (Subnet Mask Register) [R/W, 0x84 - 0x87] This register sets up the subnet mask to be used in the system, which is required to be set up before executing Sys_Init command. oGpGjG~GO~pSGpUPG X] SHAR (Source Hardware Address Register) [R/W, 0x88 - 0x8D] This register sets up the HA to be used in the system, which is required to be set up before executing Sys_Init command. SIPR (Source IP Address Register) [R/W, 0x8E - 0x91] This register sets up the IP to be used in the system, which is required to be set up before executing Sys_Init command. IRTR (Initial Retry Time-value Register) [R/W, 0x92 - 0x93] This register sets up the timer value for initial re-transmission when using the TCP, and timer value 1 is equivalent to 100us. Value 0x03E8 0x07D0 0x0FA0 Timer (ms) 100 200 400 RCR (Retry Count Register) [R/W, 0x94] This register assigns the number of retry when re-transmission occurs, and timeout interrupt occurs when retransmission exceeds the number of retry. RMSR (Rx data Memory Size Register) [R/W, 0x95] This register allocates 8KB of received memory for each channel. CH3 S1 S0 S1 CH2 S0 S1 CH1 S0 S1 CH0 S0 S1 0 0 1 1 S0 0 1 0 1 Memory size 1KB 2KB 4KB 8KB 2 bits of S1, S0 are allocated for each channel, and the memory for receiving is allocated according to the set-up value as shown in the table above. oGpGjG~GO~pSGpUPG X^ TMSR (Tx data Memory Size Register) [R/W, 0x96] This register allocates 8KB of transmitted memory for each channel. CH3 S1 S0 S1 CH2 S0 S1 CH1 S0 S1 CH0 S0 S1 0 0 1 1 S0 0 1 0 1 Memory size 1KB 2KB 4KB 8KB 2 bits of S1,S0 are allocated for each channel, and the memory for sending is allocated according to the setup value as shown in the table above. 3. Pointer Registers In order to read pointer registers, the shadow register of the corresponding pointer needs to be read and time delay of Tx_CLK * 4 is required before reading the corresponding pointer register. (Access by W3100 MCU I/F is based on 1Byte unit, but the pointer register is comprised of 4Bytes. Therefore, shadow register is used in order for MCU to properly read 4Byte pointer.) To write, no access to the shadow register or time delay is necessary. Shadow Registers C0_SRW_PR C0_SRR_PR C0_STA_PR C1_SRW_PR C1_SRR_PR C1_STA_PR C2_SRW_PR C2_SRR_PR C2_STA_PR C3_SRW_PR C3_SRR_PR C3_STA_PR C0_STW_PR Address 0x1E0 0x1E1 0x1E2 0x1E3 0x1E4 0x1E5 0x1E6 0x1E7 0x1E8 0x1E9 0x1EA 0x1EB 0x1F0 Applicable Pointer Registers C0_ RW_PR C0_ RR_PR C0_ TA_PR C1_ RW_PR C1_ RR_PR C1_ TA_PR C2_ RW_PR C2_ RR_PR C2_ TA_PR C3_ RW_PR C3_ RR_PR C3_ TA_PR C0_ TW_PR oGpGjG~GO~pSGpUPG X_ C0_STR_PR C1_STW_PR C1_STR_PR C2_STW_PR C2_STR_PR C3_STW_PR C3_STR_PR 0x1F1 0x1F3 0x1F4 0x1F6 0x1F7 0x1F9 0x1FA C0_ TR_PR C1_ TW_PR C1_ TR_PR C2_ TW_PR C2_ TR_PR C3_ TW_PR C3_ TR_PR RW_PR (Rx Write Pointer Register) [R/W, C0 : 0x10 - 0x13, C1 : 0x1C - 0x1F, C2 : 0x28 - 0x2B, C3 : 0x34 - 0x37] Included in each channel, this register displays the data end pointer when receiving data. The register is managed internally by W3100A and increases according to the size of the data received. MCU receives and processes the data from Rx Read Pointer to Rx Writer Pointer of the corresponding channel. RR_PR (Rx Read Pointer Register) [R/W, C0 : 0x14 - 0x17, C1 : 0x20 - 0x23, C2 : 0x2C - 0x2F, C3 : 0x38 - 0x3B] Included in each channel, this register displays the data start pointer when receiving data. After processing the received data, MCU updates Rx Read Pointer as the pointer of the processed data and releases Recv Command. TW_PR (Tx Write Pointer Register) [R/W, C0 : 0x40 - 0x43, C1 : 0x4C - 0x4F, C2 : 0x58 - 0x5B, C3 : 0x64 - 0x67] Included in each channel, this register displays the data end pointer of the data to be transmitted when transmitting data. For transmission, MCU writes the data to be transmitted from Tx Write Pointer of the corresponding channel, and Tx Write Pointer needs to be updated with a new value after the data is copied. Transmission is made after executing the Send command. TR_PR (Tx Read Pointer Register) [R/W, C0 : 0x44 - 0x47, C1 : 0x50 - 0x53, C2 : 0x5C - 0x5F, C3 : 0x68 - 0x6B] Included in each channel, this register displays the current working pointer of the data to be transmitted when transmitting data. The register, used internally in W3100A, displays the pointer to start transmission when transmission is made by send command. oGpGjG~GO~pSGpUPG X TA_PR (Tx Ack Pointer Register) [R/W, C0 : 0x18 - 0x1B, C1 : 0x24 - 0x27, C2 : 0x30 - 0x33, C3 : 0x3C - 0x3F] Included in each channel, this register displays the start pointer of the data to be transmitted when transmitting data. Driver uses this register and Tx Write Pointer to calculate free size of Tx Buffer. In other words, the difference in value of Tx Write Pointer and Tx Ack Pointer is the buffer size being used. 4. Channel Registers SSR (Socket State Register) [R, C0 : 0xA0, C1 : 0x B8, C2 : 0x D0, C3 : 0x E8] Displays the socket state of the corresponding channel. Value 0x00 0x01 0x02 0x03 State SOCK_CLOSED SOCK_ARP SOCK_LISTEN SOCK_SYNSENT Meaning Socket is closed Standing by for reply after transmitting ARP Request Standing by for connection set-up to the client when acting in passive mode Standing by for SYN,ACK after transmitting SYN for connection set-up when acting in active mode Connection set-up is complete after SYN,ACK is received and ACK is transmitted in active mode SYN,ACK is being transmitted after receiving SYN from the client in listen state, passive mode Connection set-up is complete in active, passive mode Connection being terminated Connection being terminated Connection being terminated Connection being terminated Connection being terminated Connection being terminated Connection is being terminated after receiving reset packet from the peer Socket initializing Applicable channel is initialized in UDP mode Applicable channel is initialized in IP layer RAW mode Standing by for reply after transmitting ARP request packet to the destination for UDP transmission Data transmission in progress in UDP or RAW mode W3100A initialized in MAC layer RAW mode 0x04 SOCK_SYNSENT_ACK 0x05 SOCK_SYNRECV 0x06 0x07 0X08 0X09 0X0A 0X0B 0X0C 0X0D 0X0E 0X0F 0X10 0X11 SOCK_ESTABLISHED SOCK_CLOSE_WAIT SOCK_LAST_ACK SOCK_FIN_WAIT1 SOCK_ FIN_WAIT2 SOCK_CLOSING SOCK_TIME_WAIT SOCK_RESET SOCK_INIT SOCK_UDP SOCK_RAW SOCK_UDP_ARP 0X12 0X13 SOCK_UDP_DATA SOCK_RAW_INIT oGpGjG~GO~pSGpUPG YW SOPR (Socket Option and Protocol Register) [R/W, C0 : 0xA1, C1 : 0x B9, C2 : 0x D1, C3 : 0x E9] This register sets up socket option or protocol of the corresponding channel. 7 Broadcast/ ERR 6 NDTimeout/ B 5 NDAck 4 SWS/ P 3 2 Protocol 1 Protocol 0 Protocol Bit D0 D1 D2 Symbol Protocol Description Sets up corresponding channel in TCP, UDP, IP Layer RAW mode or MAC Layer RAW mode Value 000 001 010 011 100 Closed SOCK_STREAM(TCP) SOCK_DGRAM(UDP) SOCK_IPL_RAW(IP Layer RAW Mode) SOCK_MACL_RAW(MAC Layer RAW Mode) Meaning D3 D4 SWS/P Reserved Silly Window Syndrome `0': prevents Silly Window Syndrome when using TCP `1': does not prevent Silly Window Syndrome when using TCP When using MAC Layer RAW mode, promiscuous packet (packet with specific MAC address) can be received by when C0_SOPR sets the bit as `1' D5 NDAck No Delayed ACK `0': uses delayed ACK `1': does not use delayed ACK - ACK is transmitted immediately upon receiving the data packet D6 NDTimeout/B No Dynamic Timeout `0': uses dynamic timeout during operation to set up timeout value regardless of the set-up value `1': activates by using the timeout value as set up in Timeout Value When using MAC Layer RAW mode, broadcast packet can be received by when C0_SOPR sets the bit as `1' D7 Broadcast/ERR Broadcast packet is received and transmitted in IP Layer RAW mode When using MAC Layer RAW mode, error packet can be received by when C0_SOPR sets the bit as `1' oGpGjG~GO~pSGpUPG YX DIR (Destination IP Address Register) [R/W, C0 : 0xA8 - 0xAB, C1 : 0xC0 - 0xC3, C2 : 0xD8 - 0xDB, C3 : 0xF0 - 0xF3] This register sets the Destination IP Address of each channel to be used in setting the TCP connection. active mode, IP address needs to be set before executing the Connect command. sets up the connection and then updates as peer IP internally. In In passive mode, W3100A DPR (Destination Port Register) [R/W, C0 : 0xAC - 0xAD, C1 : 0xC4 - 0xC5, C2 : 0xDC - 0xDD, C3 : 0xF4 - 0xF5] This register sets the Destination Port number of each channel to be used in setting the TCP connection. active mode, port number needs to be set before executing the Connect command. W3100A sets up the connection and then updates as peer port number internally. In In passive mode, SPR (Source Port Register) [R/W, C0 : 0xAE - 0xAF, C1 : 0xC6 - 0xC7, C2 : 0xDE - 0xDF, C3 : 0xF6 - 0xF7] This register sets the Source Port number for each channel when using TCP or UDP mode, and the set-up needs to be made before executing the Sock_Init Command. IPR (IP Protocol Register) [R/W, C0 : 0xB0, C1 : 0xC8, C2 : 0xE0, C3 : 0xF8] This IP Protocol Register is used to be set up at the Protocol Field of IP Header when executing the IP Layer RAW Mode, and the set-up needs to be made before executing the Sock_Init Command. TOSR (TOS Register) [R/W, C0 : 0xB1, C1 : 0xC9, C2 : 0xE1, C3 : 0xF9] This register is used to be set up at the TOS (Type Of Service) Field of IP Header, and the set-up needs to be made before executing the Sock_Init Command. MSSR (MSS Register) [R/W, C0 : B2 - 0xB3, C1 : 0xCA - 0xCB, C2 : 0xE2 - 0xE3, C3 : 0xFA - 0xFB] This register is used for MSS (Maximum Segment Size) of TCP, and the register displays MSS set by the other party when TCP is activated in Passive Mode. oGpGjG~GO~pSGpUPG YY Internal Memory and Registers W3100A Top level Memory Map WWWWWG Control registers WWYWWG Not used W[WWWG Tx data buffer W]WWWG Rx data buffer W_WWWG W3100A internal register and memory are comprised of 512 byte Control Registers and 16KB data buffer as displayed in the diagram above. 0x0000 ~ 0x00FF: Space for Control Registers 0x0100 ~ 0x01FF: Space for Shadow Registers 0x0200 ~ 0x3FFF: Not used (This space can be used by other devices) 0x4000 ~ 0x5FFF: Tx Data Buffer 0x6000 ~ 0x7FFF: Rx Data Buffer Tx data buffer is the memory used for MCU transmission, and MCU can execute `write' but cannot execute `read'. Rx data buffer is the memory used for MCU reception, and MCU can execute `read' but cannot oGpGjG~GO~pSGpUPG YZ execute `write'. In order to verify the active status of Tx data buffer and Rx data buffer, MCU can execute In memory both write and read by setting the memory test mode (setting up of C1_CR memory test bit). test mode, however, W3100A cannot execute proper transmission and reception of data. must be terminated for normal operation of W3100A. Memory test mode oGpGjG~GO~pSGpUPG Y[ Description of Functions 1. Initialization of W3100A In order to use W3100A, the basic registers that are required to run W3100A need to be set up. The basic registers include GAR (Gateway Address Register), SMR (Subnet Mask Register), SHAR (Source Hardware Address Register), and SIPR (Source IP Address Register). GAR, SMR and SIPR are the network information on which W3100A is operated, and the registers need to be set according to the operating environment. SHAR is the Hardware address to be used at the MAC layer of W3100A, and the address already provided to the manufacturer is used. After appropriately setting up above registers, W3100A can activate in the network by executing the sys_init command. Activation can be verified by using Ping (ICMP Echo request). 2. TCP Protocol TCP is a connection-oriented protocol. By using three-way handshaking method in executing the connection set-up and termination process, reliable data transmission and reception are assured. TCP Initialization Process In order to use W3100A TCP, the protocol field of the corresponding channel's Cx_SOPR (Socket Option/Protocol Register of Channel x) needs to be set up as SOCK_STREAM(0x01). After the channel is activated by sock_init command, Cx_TW_PR (Tx Write Pointer Register of Channel x), Cx_TR_PR (Tx Read Pointer Register of Channel x), and Cx_TA_PR (Tx Ack Pointer Register of Channel x) need to be initialized with same value. TCP Connection Set-up Process In W3100A, the TCP connection process as directed by Connect or Listen command is processed internally. Sending SYN Packet as directed by Connect command is called active open, and standing by for SYN Packet from peer as directed by Listen command is called passive open. Active open. TCP Client mode that knows the IP address and port number of the destination, and the connection set-up is made ahead. oGpGjG~GO~pSGpUPG Y\ starting point CLOSED cmd : sys_init, close cmd : sock_init INIT Timeout recv : RST cmd : connect send : ARP request ARP SYNSENT recv : ARP reply send : SYN ESTABLISHED recv : SYN, ACK send : ACK Above diagram illustrates the connection set-up process using active open. through the socket status register of the corresponding channel. a. CLOSED state: channel is initialized by executing sys_init or close command Each status can be verified b. INIT state: sets the port number (source port register) to be used in the channel and activates the channel by executing the sock_init command c. ARP state: In order to set up connection, MCU sets the Destination IP, Destination Port register and executes the connect command. request packet. Based on this command, W3100A changes to this state and transmits ARP When ARP reply packet is received from the peer under this state, it changes to SYNSENT In case no reply is received from the peer, re-transmission is made. state and transmits SYN packet. When no reply is received within the designated timeout duration, timeout occurs and it changes to CLOSED state. d. SYNSENT state: In this state, W3100A transmits SYN packet and stands by to receive SYN,ACK packet from the peer. In case appropriate SYN,ACK packet is received, W3100A transmits ACK packet and In case no appropriate When no reply is Also, if completes the connection set-up to become changed to ESTABLISHED state. SYN,ACK packet is received from the peer, re-transmission of SYN Packet is made. received within the designated timeout duration, timeout occurs and it changes to CLOSED state. the peer has no application standing by in passive mode, the peer receives RST packet and changes to CLOSED state. Passive open. In TCP Server mode, stands by for connection set-up from the peer under the Listen command, and the connection set-up is accepted when requested. oGpGjG~GO~pSGpUPG Y] starting point CLOSED cmd : sys_init, close cmd : sock_init INIT cmd : listen Timeout recv : RST LISTEN SYNRCVD recv : ACK recv : SYN send : SYN, ACK ESTABLISHED a. CLOSED state: channel is initialized by executing sys_init or close command b. INIT state: sets the port number (source port register) to be used in the channel and activates the channel by executing the sock_init command c. LISTEN state: stands by for connection set-up from the peer. When SYN packet for the corresponding port is received from the peer, SYN,ACK packet is transmitted and changes to SYNRCVD state. d. SYNRCVD state: SYN,ACK packet is transmitted and stands by for ACK from the peer. When reply from the peer is received, it changes to ESTABLISHED state, and when no reply is received, SYN,ACK Packet is re-transmitted and changes to CLOSED state upon occurrence of timeout or receipt of RST packet. TCP Connection Termination Process In line with the connection set-up process, TCP connection termination process also uses three-way handshaking method. Sending FIN after receiving Close command from the application is called active close, and closing after receiving FIN from the peer is called passive close. cmd : close send : FIN ESTABLISHED recv : FIN send : ACK FIN_WAIT1 recv : ACK recv : FIN send : ACK recv : FIN, ACK send : ACK recv : FIN send : ACK active close CLOSING recv : ACK CLOSE_WAIT cmd : close send : FIN FIN_WAIT2 TIME_WAIT LAST_ACK recv : ACK passive close CLOSED oGpGjG~GO~pSGpUPG Y^ Active close After completing data transmission and reception, the application uses the close command to terminate the connection set-up. When the connection is terminated under the close command in such ESTABLISHED state, it is called active close, and the process is illustrated in the left-hand side of the diagram above. FIN_WAIT1 state: changes from the established state under the close command and transmits FIN packet. Changes to FIN_WAIT2 when ACK for FIN is received fro the peer. Transmits ACK and changes to CLOSING state when FIN is received from the peer. FIN,ACK is received. Transmits ACK and changes to TIME_WAIT when In case of no reply, re-transmission is made, and if no reply is received until timeout occurs, changes to CLOSED state. FIN_WAIT2 state: stands by for FIN from the peer. In this state, W3100A does not receive data from the This is because peer, and if data is received, connection set-up is immediately terminated through RST. W3100A does not process additional data in half-close state. CLOSING state: produced when the application closes simultaneously. ACK is received from the peer. TIME_WAIT state: viewed as 2MSL (Maximum Segment Lifetime) WAIT State by TCP. Changes to TIME_WAIT when In case FIN is In case TCP resent when the peer cannot receive ACK, there is a function where TCP resends the last ACK. connection is in 2MSL wait state, there is another function where other client, server is blocked from using this connection. In W3100A, considering the limited resource and for efficient use of the channel, it changes from this state to CLOSED state without waiting. Passive close In passive close, FIN is received from the peer to close in the ESTABLIHSED state as illustrated in the righthand side of the above diagram. CLOSE_WAIT state: changed from ESTABLISHED state by receiving FIN from the peer. for FIN and creates closed interrupt at MCU. Transmits ACK By processing the interrupt, MCU executes the close But, if data to be sent still are left, that is command to W3100A and completes the connection close. TW_PR value is not equal to TA_PR value, you should not issue the close command but wait until timeout occurs or ignore close procedure and make progress next step like sock_init command. LAST_ACK state: when close command is handed down by MCU, FIN is transmitted and stands by for ACK. If no ACK is received, FIN Packet is re-transmitted. If no reply is received until timeout occurs, it changes to CLOSED state. TCP Data Transmission and Reception Unlike UDP, TCP data transmission and reception is possible only after the connection set-up is made. W3100A has exclusive memory for data transmission and reception, 8KB for transmission and 8KB for reception. This memory can be set up as 1KB, 2KB, 4KB and 8KB by using RMSR (Rx data Memory Size Register) and TMSR (Tx data Memory Size Register). oGpGjG~GO~pSGpUPG Y_ TCP Transmission Memory Size Set-up W3100A transmission memory is comprised of 8KB in total, and the size can be assigned for each channel through TMSR register. An example of TMSR and each memory size is illustrated in the diagram below. When the memory size from channel 0 exceeds 8KB, all ensuing memory is ignored. {GtGh 0x2000 0x2000 0x2000 CH3 0x1800 CH3 CH2 0x1000 0x1000 CH0 0x1000 CH1 0x0800 CH2 0x0800 CH0 0x0000 YriGGGG TMSR <= 0x55 CH1 0x0400 CH0 0x0000 0x0000 8KB allocated at channel 0 TMSR <= 0x03 Remaining channels are not used 1KB, 1KB, 2KB, 4KB allocated TMSR <= 0x90 TCP Data Transmission Process TCP starting point ESTABLISHED TCP send cal FBS(free buffer size) No Cx_TW_PR = A Cx_TA_PR = A FBS <= Cx_TW_PR Cx_TA_PR FBS > SDS(send data size) Yes Yes Send bit == '1' write data from Cx_TW_PR No check previous send comand write data Cx_TW_PR <= update Cx_TW_PR Cx_TW_PR + SDS send command In order to execute W3100A TCP transmission, 4Byte pointer of Cx_TW_PR (Tx Write Pointer Register of Channel x) and Cx_TA_PR (Tx Ack Pointer Register of Channel x) is used. Cx_TW_PR is the pointer that writes the data to be transmitted from MCU, and Cx_TA_PR is the pointer that completed W3100A transmission. Cx_TW_PR and Cx_TA_PR become equal after connection set-up is made. In active open, they are equally initialized under the sock_init command from MCU. In passive open, one is initialized by oGpGjG~GO~pSGpUPG Y the other. The difference between the pointers become the actual FBS (free buffer size). Data is recorded from Cx_TW_PR according to such size, and when the data recording is complete, Cx_TW_PR is increased according to the size of the recorded data and executes the send command. Pointer Management during TCP Transmission 0x2000 CH3 0x1800 CH2 0x1000 CH1 0x0800 CH0 0x0000 2KB allocated at each channel 0x0000 Since transmission memory is 2KB, mask is 0x000007FF 0x0200 Tx data 0x0200 Cx_TA_PR Cx_TW_PR and Cx_TA_PR are equal (0x00123000 assumed) 0x0800 0x0800 0x0800 Cx_TW_PR is increased to 0x00123200 (MCU) Cx_TW_PR Cx_TA_PR is increased to 0x00123200 0x0000 0x0000 (W3100A) When MCU records the transmission When W3100A data for transmission and Cx_TW_PR completes the is increased transmission Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. TCP Reception Memory Size Set-up Receiving memory of W3100A has the same structure of the transmission memory and operated in same method. The memory is comprised of 8KB in total, and the size can be assigned for each channel through RMSR (Rx data Memory Size register). below. When the memory size from channel 0 exceeds 8KB, all ensuing memory is ignored. An example of RMSR and each memory size is illustrated in the diagram Reception Memory Allocation 0x2000 0x2000 0x2000 CH3 0x1800 CH3 CH2 0x1000 0x1000 CH0 0x1000 CH1 0x0800 CH2 0x0800 CH0 0x0000 2KB allocated at each channel RMSR <= 0x55 CH1 0x0400 CH0 0x0000 0x0000 8KB allocated at channel 0 RMSR <= 0x03 Remaining channels are not used 1KB, 1KB, 2KB, 4KB allocated RMSR <= 0x90 oGpGjG~GO~pSGpUPG ZW TCP Data Reception Process TCP starting point ESTABLISHED recv LEN cal RDS(recv data size) No Cx_RW_PR = A Cx_RR_PR= A TCP receive RDS <= Cx_RW_PR Cx_RR_PR RDS >= recv LEN Yes read data from read data Cx_RR_PR Cx_RR_PR <= update Cx_RR_PR Cx_RR_PR + LEN recv command TCP data reception by W3100A is illustrated in the above diagram. In W3100A, when data is received from the peer, the data is recorded as reception memory from Cx_RW_PR (Rx Write Pointer Register of Chnnel x), Cx_RW_PR is increased according to the size of the received data when the reception is complete, and then MCU is interrupted to report a data reception. Through interrupt or polling, MCU compares Cx_RW_PR and Cx_RR_PTR (Rx Read Pointer Register of Channel x), and when data reception is observed, the size of the received data is first calculated and Cx_RR_PR is increased after the data is read and processed from Cx_RR_PR. the received data is complete. Finally, recv command is executed to report W3100A that the processing of Pointer Management during TCP Reception 0x2000 CH3 0x1800 CH2 0x1000 CH1 0x0800 CH0 0x0000 2KB allocated at each channel 0x0000 Since reception memory is 2KB, mask is 0x000007FF 0x0280 0x0280 0x0800 0x0800 Cx_RW_PR and Cx_RR_PR are equal (0x00123280 assumed) 0x0400 Rx Data 0x0280 Cx_RR_PR 0x0000 When Cx_RW_PR is increased by receiving data from the peer at W3100A 0x0800 Cx_RW_PR is increased to 0x00123400 (W3100A) 0x0400 Cx_RR_PR is increased to 0x00123400 (MCU) Cx_RW_PR 0x0000 When MCU completes the processing of the received data and Cx_RR_PR is increased Above diagram illustrates the change in Cx_RW_PR and Cx_RR_PR when actual data is received after 2KB of reception memory is set at CH0. oGpGjG~GO~pSGpUPG ZX TCP Retry Time Adjustment W3100A uses IRTR (Initial Retry Time-value Register) and RCR (Retry Count Register) to adjust the timer to be used in re-transmission of TCP. TCP re-transmission is executed when the initial retry timer expires, and the retry timer is reset at the value of * 2. Such a process is repeated according to the RCR value, and in the last retry, timeout interrupt occurs and then gives up. Formula of timeout value: IRTR: Initial Retry Time-value Register RCR: Retry Count Register IRTR * 100us = start timeout second Total timeout value until give-up = (IRTR * 100us) *(2RCR-1) Internally, the default value of IRTR is 0x07D0 and RCR is 0x06, where initial retry takes place at 200ms and the retry frequency becomes 6. Therefore, unless these registers are revised, retry is made at 200ms, 600ms, 1400ms, 3000ms, 6200ms, 12600ms each and gives up at the final 12600ms. 3. UDP Protocol UDP is a connectionless protocol. lesser load. No connection set-up or termination process is needed, thereby creating UDP Initialization Process In order to use UDP of W3100A, the Cx_SOPR (Socket Option/Protocol register of Channel x) protocol field of the corresponding channel needs to be set as SOCK_DGRAM(0x02) before socket initialization. TCP, data transmission and reception is possible at UDP without any connection set-up process. Unlike UDP Data Transmission and Reception UDP transmission is activated similarly to TCP. All data received at its port can be received, and MCU needs to analyze the header information of the data to verify transmitting IP and port to confirm the corresponding data before processing. Set-up of transmission and reception memory size is identical to TCP. UDP Data Transmission UDP transmission is activated similarly to TCP. copying and Cx_TW_PR are identical. Calculating the free buffer size of the memory, data The difference is the usage of Cx_TR_PR instead of Cx_TA_PR. In other words, if the destination IP and Another difference is that destination IP and port need to be set. oGpGjG~GO~pSGpUPG ZY port set prior to this transmission are different to the destination IP and port to be used for the transmission, the values need to be updated before executing the send command. UDP starting point UDP UDP sendto cal FBS(free buffer size) No Cx_TW_PR = A Cx_TR_PR = A FBS <= Cx_TW_PR Cx_TR_PR FBS > SDS(send data size) Yes Yes Send bit == '1' No check previous send comand write data from Cx_TW_PR write data Cx_TW_PR <= update Cx_TW_PR Cx_TW_PR + SDS if need, update DIP, DPort send command Pointer Management during UDP Transmission 0x2000 CH3 0x1800 CH2 0x1000 CH1 0x0800 CH0 0x0200 Tx data 0x0200 0x0800 0x0800 Cx_TW_PR and Cx_TA_PR are equal (0x00123000 assumed) 0x0800 Cx_TW_PR is increased to 0x00123200 (MCU) Cx_TW_PR Cx_TR_PR is increased to Cx_TR_PR 0x00123200 0x0000 0x0000 0x0000 0x0000 (W3100A) When W3100A When MCU records the 2KB allocated at Since transmission memory is completes the each channel 2KB, mask is 0x000007FF transmission data for transmission transmission and Cx_TW_PR is increased Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. UDP Data Reception W3100A's UDP reception is similar to TCP reception. The difference is that the header information for The header is structured as below. UDP processing is included in the received data in addition to the data. TLEN 0 2 SIP 4 6 SPort 8 UDP data xx oGpGjG~GO~pSGpUPG ZZ The header is comprised of (1) TLEN Field displaying the size of 2Byte Header + data, (2) 4Byte SIP displaying the sender IP that transmitted UDP data, and (3) SPort displaying the sender Port. such information to determine whether the data needs to be processed by MCU before processing. UDP starting point UDP recv LEN cal RDS(recv data size) No MCU uses Cx_RW_PR = A Cx_RR_PR = A UDP receivefrom RDS <= Cx_RW_PR Cx_RR_PR RDS >= recv LEN read data from Cx_RR_PR Yes read data processing UDP data Cx_RR_PR <= Cx_RR_PR + update Cx_RR_PR LEN recv command Above diagram illustrates the MCU processing flow for UDP data. UDP data, the basic flow is identical to TCP reception. Excluding the header processing for the UDP Reception Memory Management for Each Channel 0x2000 0x0800 CH3 0x1800 CH2 0x1000 CH1 0x0800 0x0200 CH0 0x0000 0x0000 Since reception 2KB allocated at each channel memory is 2KB, mask is 0x000007FF 0x0000 0x0800 Cx_RW_PR and Cx_RR_PR are equal (0x00123200 assumed) 0x0400 Rx Data 0x0200 head 0x0800 Cx_RW_PR is increased to 0x00123400 (W3100A) 0x0580 0x0400 0x0800 Cx_RW_PR is increased to 0x00123580 (W3100A) 0x0580 0x0400 0x0800 Cx_RW_PR 0x0580 Cx_RW_PR Rx Data head Rx Data head Rx Data 0x0200 head Cx_RR_PR 0x0000 0x0200 Cx_RR_PR 0x0000 Cx_RR_PR is increased to 0x00123400 (MCU) 0x0000 Cx_RR_PR is increased to 0x00123580 (MCU) When Cx_RW_PR is increased by receiving data from the peer at W3100A When Cx_RW_PR is increased by receiving data from the peer at W3100A When MCU completes When MCU completes the processing of the the processing of the received data and received data and Cx_RR_PR is increased Cx_RR_PR is increased At UDP reception buffer, many different data may exist between Cx_RW_PR and Cx_RR_PR. the header information is used to differentiate and process such data. where 2 UDP's receive the data and processed by MCU. Therefore, Above diagram illustrates the process oGpGjG~GO~pSGpUPG Z[ 4. IP Layer RAW Mode W3100A's IPL_RAW(IP Layer RAW) mode is used in processing protocols (e.g., ICMP, etc.) other than TCP and UDP as provided by W3100A. IPL_RAW Mode Initialization Process In order to use W3100A's IPL_RAW Mode, the protocol value of the IP Layer to be used (e.g., 0x01 in case of ICMP) needs to be set as Cx_IPR (IP Protocol Register of Channel x), and the Cx_SOPR (Socket Option/Protocol register of Channel x) protocol field of the corresponding channel needs to be set as SOCK_IPL_RAW(0x03) before socket initialization (sock_init command). and reception is possible when the corresponding channel is initialized. As in UDP, data transmission IPL_RAW Mode Data Transmission and Reception Transmission in IPL_RAW Mode is activated similarly to UDP, and the reception is made for the same Protocol data as Cx_IPR. IPL_RAW Mode Data Transmission IPL_RAW starting point Cx_TW_PR = A IPL_RAW Cx_TR_PR = A IPL_RAW sendto FBS <= cal FBS(free Cx_TW_PR buffer size) Cx_TR_PR No FBS > SDS(send data size) Yes Yes Send bit == '1' No check previous send comand write data from Cx_TW_PR write data Cx_TW_PR <= update Cx_TW_PR Cx_TW_PR + SDS if need, update DIP send command For reception in IPL_RAW Mode, calculating the free buffer size of the reception memory, data copying and usage of Cx_TW_PR, Cx_TR_PR are identical to UDP, and the destination IP needs to be set. however, no port needs to be set. Unlike UDP, As in UDP, if the destination IP set prior to this transmission is different to the destination IP to be used for the transmission, the value need to be updated before executing the send command. oGpGjG~GO~pSGpUPG Z\ IPL_RAW Transmission Pointer Management 0x2000 CH3 0x1800 CH2 0x1000 CH1 0x0800 CH0 0x0000 2KB allocated at each channel 0x0000 Since transmission memory is 2KB, mask is 0x000007FF 0x0200 Tx data 0x0200 Cx_TR_PR is increased to 0x00123200 (W3100A) Cx_TW_PR and Cx_TR_PR are equal (0x00123000 assumed) 0x0800 0x0800 0x0800 Cx_TW_PR is increased to 0x00123200 (MCU) Cx_TW_PR Cx_TR_PR 0x0000 0x0000 When MCU records the When W3100A completes transmission data for transmission the transmission and Cx_TW_PR is increased Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. IPL_RAW Mode Data Reception Reception in W3100A's IPL_RAW Mode is similar to UDP reception. As in UDP, header information is included in the received data in addition to the data, and the header is structure as below. TLEN 0 2 SIP 6 IP RAW data xx The header information IPL_RAW mode contains (1) TLEN identical to UDP TLEN displaying the total length of data size + header length, and (2) 4Byte SIP displaying the sender IP that transmitted UDP data. Both are used with Cx_RW_PR and Cx_RR_PR to process the received data. identically to the UDP reception data processing. The process is made 5. MAC Layer RAW Mode In MACL_RAW (MAC Layer RAW) mode, W3100A is used as other general NIC (Network Interface Controller), and W3100A's TCP/IP module is not used in this mode. When TCP/IP is used through W3100A, the number of channels is limited to 4. For systems using more than 4 channels simultaneously, W3100A uses this mode and S/W TCP/IP can be processed in the higher drive. If MAC Layer RAW Mode is used, W3100A uses Channel 0 only and other channels are ignored. oGpGjG~GO~pSGpUPG Z] MACL_RAW Mode Initialization Process In MACL_RAW Mode, data transmission and reception is possible after the protocol field of C0_SOPR (Socket Option/Protocol register of Channel 0) is set as SOCK_MACL_RAW(0x04) and by using sock_init command of channel 0. Option values to be set at C0_SOPR include ERR, B, P bit. ERR bit allows the reception of Packet with error, B bit allows the reception of Broadcast Packet, and P bit allows the reception of Promiscuous Packet (Packet with specific MAC address). MACL_RAW Mode Data Transmission and Reception Transmission in MACL_RAW Mode is activated similarly to UDP, and the data reception is made according to C0_SOPR. MACL_RAW Mode Data Transmission Management MACL_RAW Mode's transmission memory management uses a single Channel only, that is Channel 0, and uses 8KB of transmission memory. MACL_RAW Transmission Memory Management 0x2000 0x2000 0x2000 C0_TW_PR and C0_TR_PR are equal (0x00000000 assumed) C0_TW_PR is increased to 0x00000200 (MCU) C0_TW_PR 0x0200 Tx Data 0x0200 0x0000 Since transmission memory is 8KB, mask is 0x00001FFF C0_TR_PR 0x0000 0x0000 When MCU records the transmission data for transmission and C0_TW_PR is increased C0_TR_PR is increased to 0x00000200 (W3100A) MACL_RAW Mode Data Transmission For transmission in MACL_RAW Mode, calculating the free buffer size of the transmission memory, data copying, and usage of C0_TW_PR, C0_TR_PR are identical to UDP, but unlike UDP, no destination IP and Port set up is needed. In other words, in MACL_RAW Mode, all protocol processing is made by MCU, and such information is included in the transmission Frame. oGpGjG~GO~pSGpUPG Z^ MACL_RAW sendto MACL_RAW starting point C0_TW_PR = A MACL_RAW C0_TR_PR = A cal FBS(free buffer size) FBS > SDS(send data size) Yes FBS <= C0_TW_PR C0_TR_PR No Yes Send bit == '1' No check previous send comand write data from C0_TW_PR write data C0_TW_PR <= update C0_TW_PR C0_TW_PR + SDS send command MACL_RAW Mode Data Reception Management MACL_RAW Reception Memory Management 0x2000 0x2000 C0_RW_PR and C0_RR_PR are equal (0x00000200 assumed) 0x0400 Rx Data 0x0200 head 0x2000 C0_RW_PR is increased to 0x00000400 (W3100A) 0x0580 0x0400 0x2000 C0_RW_PR is increased to 0x00000580 (W3100A) 0x0580 0x0400 0x2000 C0_RW_PR 0x0580 C0_RW_PR Rx Data head Rx Data head 0x0200 Rx Data 0x0200 head C0_RR_PR 0x0000 0x0200 C0_RR_PR 0x0000 C0_RR_PR is increased to 0x00000400 (MCU) 0x0000 C0_RR_PR is increased to 0x00000580 (MCU) 0x0000 0x0000 When C0_RW_PR is When C0_RW_PR is Since reception memory is 8KB, increased by receiving data increased by receiving data mask is 0x00001FFF from the peer at W3100A from the peer at W3100A When MCU completes the processing of the received data and C0_RR_PR is increased When MCU completes the processing of the received data and C0_RR_PR is increased MACL_RAW Mode's Reception memory management uses 1 channel only, therefore all 8KB is allocated to Channel 0. Above diagram illustrates the processing of 2 data after C0_WR_PR and C0_RR_PR are equally initialized as 0x00000200. MACL_RAW Mode Data Reception In W3100A's MACL_RAW Mode, the reception of the set packets are made according to the receive options as set at C0_SOPR. As in UDP, header information is included in the received data in addition to the data, and the header is structure as below. oGpGjG~GO~pSGpUPG Z_ TLEN 0 2 STT 3 MAC RAW data As shown in the above diagram, the header information IPL_RAW mode contains (1) TLEN identical to UDP TLEN displaying the total length of data and header length, and (2) 1 Byte STT displaying the status of the received data. The description of the received data is recorded at STT Byte as below. 7 1 6 x 5 x 4 x 3 x 2 x 1 x 0 x Meaning Destination H/W Address of the received packet is identical to SHAR (Source H/W Address Register) x x x x 1 x x 1 x x x x x x x x Reception of Broadcasting Packet Reception of Packet with Error MACL_RAW starting point C0_RW_PR = A MACL_RAW C0_RR_PR = A MACL_RAW recv LEN receivefrom RDS <= cal RDS(recv C0_RW_PR data size) C0_RR_PR No RDS >= recv LEN read data from C0_RR_PR Yes read data processing MACL_RAW data C0_RR_PR <= C0_RR_PR + update C0_RR_PR LEN recv command As in UDP, the reception module uses C0_RW_PR and C0_RR_PR to process the received data. The process is identical to UDP received data process. oGpGjG~GO~pSGpUPG Z Application Information W3100A MCU I/F is comprised of Direct Bus I/F Mode, Indirect Bus I/F Mode, and I2C I/F Mode 1. Relationship between MCU Bus I/F Mode and Mode pin (M[2:0]) M2 0 0 0 0 1 M1 0 0 1 1 X M0 0 1 0 1 X Clocked mode External clocked mode Non-clocked mode Description Mode using a clock to analyze the MCU bus signal (default mode) Mode using an external clock to analyze the MCU bus signal Mode directly using the MCU bus signal Mode using I C Mode used at the manufacturing plant for testing Not to be used by the average user 2 I C mode Test mode 2 Refer to the timing by mode diagram for detailed access timing for each mode. (Page 50 - page 58) Considering the I/F between the MCU and W3100A, Clocked mode, External clocked mode, or Non-clocked mode can be used if Bus I/F is provided by the MCU. Timing is slightly different in each mode, and MCU bus timing also needs to be considered before selecting the mode. The first thing to consider in selecting the mode is the relationship among /CS, /RD, /WR, and Address[14:0] granted to the W3100A. If /CS is low and /RD, /WR, and Address[14:0] have valid signals over 100ns, use Clocked mode. This mode is the default mode and is suitable for most systems. However, some systems require faster access (access time of less than 100ns) to the W3100A, in which case either the External clocked mode or the Non-clocked mode should be selected. Non-clocked mode should be used in a situation where /CS granted to the W3100A drops to low as in the access timing diagram on page 54 and /RD or /WR goes low after 10ns. Otherwise, External clocked mode should be used. In the External clocked mode, the access time differs depending on the clock granted to EXT_CLK. Therefore, caution should be taken in using External clocked mode. Refer to the access timing diagram with EXT_CLK of 50MHz (page 52). Generally, Clocked mode is recommended after adjusting the access time for the W3100A to 100ns or higher (page 50), rather than using the External clocked mode. Further details about each mode are as follows: Clocked mode is used in internal functions and in the MCU I/F using the clock granted to W3100A, and the access timing may vary depending on the frequency (basic frequency: 25MHz). Clock basically uses 25MHz, but when a different frequency clock other than 25MHz is used, the access time of the MCU bus I/F and timeout occurrence time can change. In External clocked mode, the internal functions of W3100A are executed by the clock granted to the clock oGpGjG~GO~pSGpUPG [W pin, and the MCU bus I/F is activated by the External clock. In Non-clocked mode, the internal functions of W3100A are executed by the clock granted to the clock pin, and the MCU bus I/F is activated by /CS, /RD, /WR of MCU. As shown in the timing diagram, and unlike Clocked mode and External clocked mode, a timing condition exists between /CS, /RD, and /WR. I2C I/F mode is used when an MCU connected to W3100A supports I2C I/F but does not support bus I/F. The basic frequency to be used for I2C is activated by the clock granted to the clock pin and both 100KHz mode and 400KHz mode are supported. 2. Direct Bus I/F Mode. MCU /CS /WR /RD /INT D[7:0] A[14:0] /CS /WR /RD /INT ~ZXWWhG ~ZXWWhG Wh RX_CLK RXDV/CRS RXD[3:0] MII Ethernet PHY RXC TX CRS RX RXD[3:0] TXC TXE TXD[3:0] COL /LINK /FDPLX CLOCK RJ-45 TransformerG TX_CLK TXE D[7:0] TXD[3:0] A[14:0] COL /LINK /FDPLX CLOCK As illustrated in the above diagram, Direct Bus I/F mode uses a 15-bit address line and 8-bit data line, /CS, /RD, /WR, /INT, which is identical to the I/F of the existing W3100A. Since the access timing changes from Clocked mode (page 50) to External clocked mode (page 52) and to Non-clocked mode (page 54), the MCU bus access timing needs to be considered. 3. Indirect Bus I/F Mode. Indirect Bus I/F mode uses a 2-bit address line and 8-bit data line, /CS, /RD, /WR, and /INT. Of the address lines, A[14:4] is grounded as `0' and A[3:2] is pulled up (4.7 k) to `1'. ~ZXWWhG ~ZXWWhG /CS /WR /RD /INT D[7:0] A[1:0] VCC 4.7 k A[3:2] /CS /WR /RD /INT D[7:0] A[1:0] A[14:4] RX_CLK RXDV/CRS RXD[3:0] TX_CLK TXE TXD[3:0] COL /LINK /FDPLX CLOCK Ethernet PHY RXC TX CRS RX RXD[3:0] TXC TXE TXD[3:0] COL /LINK /FDPLX CLOCK RJ-45 MCU MII TransformerG oGpGjG~GO~pSGpUPG [X A[3:2] can be set up as `1' by software after connecting the additional 4 address lines of A[3:0] and grounding the remaining A[14:4]. Registers related to indirect bus I/F mode are listed below: Address 0x0C 0x0D 0x0E 0x0F Name IDM_OR IDM_AR0 IDM_AR1 IDM_DR B7 IND_EN B6 B5 B4 B3 B2 B1 L/B B0 AUTO_INC indirect bus I/F mode address0 register indirect bus I/F mode address1 register indirect bus I/F mode data register IDM_OR (Indirect Mode Option Register) is comprised of IND_EN that determines the use of Indirect Bus I/F mode, the L/B bit that determines byte ordering during address set-up, and the AUTO_INC bit that automatically increases the address. IDM_AR0 (Indirect Mode Address0 Register) designates the higher byte of the address, and IDM_AR1 (Indirect Mode Address1 Register) designates the lower byte of the address. and IDM_AR1 varies depending upon the L/B bit set-up. IDM_DR (Indirect Mode Data Register) displays the data to be accessed. The ordering of IDM_AR0 In order to use Indirect Bus I/F mode, IND_EN of IDM_OR needs to be setup first. In order to read the internal register value of W3100A, the address of the internal register to be accessed needs to be written to IDM_AR0,1. read. In order to write the internal register value of W3100A, the address of the internal register to be accessed needs to be written at IDM_AR0,1. Later, the value can be written at IDM_DR. Later, when IDM_DR is read, the value of the register to be accessed is The L/B bit of IDM_OR that sets up the order when accessing IDM_AR0,1 functions as below: If L/B bit of IDM_OPT register = `0' MSB IDM_ADDR0(0x0D) If L/B bit of IDM_OPT register = `1' LSB IDM_ADDR0(0x0D) MSB IDM_ADDR1(0x0E) IDM_ADDR1(0x0E) LSB AUTO_INC Bit allows register access without setting IDM_AR0,1 for each access when continuous access is made, where IDM_AR0,1 is automatically incremented by 1 with each IDM_DR access. oGpGjG~GO~pSGpUPG [Y 4. I2C I/F Mode. I2C I/F uses SDA, SCL to provide serial data transmission and reception in I2C mode between MCU and W3100A. As a clock line, SCL needs to be provided by MCU, and SDA is used as the line to transfer data and address between MCU and W3100A. MCU /INT VCC VCC SCL SDA I2C Device address set-up /INT ~ZXWWhG ~ZXWWhG RX_CLK RXDV/CRS RXD[3:0] TX_CLK TXE TXD[3:0] COL /LINK /FDPLX CLOCK MII Ethernet PHY RXC TX CRS RX RXD[3:0] TXC TXE TXD[3:0] COL /LINK /FDPLX CLOCK TransformerG SCL SDA A[14:8] A[7:0] RJ-45 A simple block diagram as shown above illustrates the connection between MCU and W3100A using I2C. As illustrated above, it is recommended to set the device address for I2C by using A[14:8], provide a pull-up of 4.7 k for SCL and SDA lines externally, and then ground the remaining address A[7:0]. oGpGjG~GO~pSGpUPG [Z In order to synchronize MCU and W3100A, I2C I/F creates the condition for START before transmitting and receiving data, and the condition for STOP is created after the completion of data transmission and reception. When SDA line becomes low while SCL line is high, it becomes the signal for the condition for START. When SDA line becomes high while SCL line is high, it becomes the signal for the condition for STOP. Data Validity SDA SDA Start and Stop Definition SCL DATA STABLE DATA CHANGE DATA STABLE SCL START STOP Access method includes random read/write access for 1Byte-unit access and sequential read/write access for sequential access. RANDOM BYTE WRITE S T A R T SDA LINE M S B L S B RAM / CS WK B L S B AM CS KB L S B AM CS KB LA SC BK W R I T E DEVICE ADDRESS WORD ADDRESS0(1B) WORD ADDRESS1(1B) DATA(1B) S T O P oGpGjG~GO~pSGpUPG [[G 1Byte-unit access is functions as illustrated in the above diagram, and random byte write sends in the order of START, DEVICE ADDRESS, 2 Byte address of the actual register to be accessed, and the actual data before sending STOP. In order to set up the address of the register to be accessed, random byte read first sends START, DEVICE ADDRESS and 2 Byte register address before sending STOP. Later, once again, START, DEVICE ADDRESS is sent, actual data is read and STOP is sent. RANDOM BYTE READ S T A R T SDA LINE M S B S T A R T SDA LINE M S B L S B RAM /CS WK B L S B N O A C K L S B RAM /CS WK B R E A D L S B AM CS KB S T O P L S B A C K W R I T E DEVICE ADDRESS WORD ADDRESS0(1B) WORD ADDRESS1(1B) S T O P DEVICE ADDRESS DATA(1B) oGpGjG~GO~pSGpUPG [\G Sequential byte write sequentially sends START, DEVICE ADDRESS, 2 Byte address of the actual register to be accessed, and data to be written before sending STOP. As a result, MCU can designate the address of the data to be written once, which allows for the data to be written sequentially and the address to automatically increase by 1. SEQUENTIAL BYTE WRITE S T A R T SDA LINE M S B L S B RAM /CS WK B L S B AM CS KB L S B AM CS KB W R I T E DEVICE ADDRESS WORD ADDRESS0(1B) WORD ADDRESS1(1B) DATA(1B) DATA(1B) S T O P ......... LA SC BK M S B LA SC BK In order to set up the address of the register to be accessed, sequential byte read first sends START, DEVICE ADDRESS and 2 Byte register address before sending STOP. Later, once again, START, DEVICE ADDRESS is sent and actual DATA is sequentially read before sending STOP. Also at this time, the address automatically increases by 1. oGpGjG~GO~pSGpUPG []G SEQUENTIAL BYTE READ S T A DEVICE R ADDRESS T SDA LINE M S B S T A R T SDA LINE M S B L S B L S B W R I T E WORD ADDRESS0(1B) WORD ADDRESS1(1B) S T O P RAM / CS WK B R E A D L S B AM CS KB L S B A C K S T O P DEVICE ADDRESS DATA(1B) DATA(1B) DATA(1B) ....... RAM /CS WK B L S B M S B L S B M S B LN SO BA C K oGpGjG~GO~pSGpUPG [^G G 5. Physical Layer Interface W3100A is used for linking with an Ethernet Physical Layer Device (RealTek RTL8201, National DP83843, SMSC 83C180, 83C183, LevelOne LXT905, etc.). Such Physical Layer Devices generally use the Media Interface (MI) for configuration and the Media Independent Interface (MII) for data transfer when interfacing with the Ethernet MAC Layer. 5.1 Media Interface (MI) The MI is the serial I/F for reading/writing the internal register of the Physical Layer Device to set up or check the configuration of the Physical Layer Device, and its pin is generally denoted as MDC or MDIO. Since the W3100A does not configure or check the configuration of the Physical Layer Device through the MI, the systems equipped with the W3100A configure the Physical Layer Device using its pin (in general, SPEED, DUPLEX, Auto Negotiate, etc.), so that the W3100A can refer to the configuration status through the W3100A pins (/LINK, /SERIAL, /FDPLX). In other words, /LINK, /SERIAL, and /FDPLX pins of the W3100A must be connected to reflect the status of the Physical Layer Device. In general, the Physical Layer Device reports the network configuration status using the LED Pins, which are connected with the /LINK, /SERIAL, and /FDPLX Pin of the W3100A. Besides, depending on the systems, it may be necessary for the MCU to configure or check the configuration of the Physical Layer Device, in which case the MCU must access the Physical Layer Device directly through the MI. 5.2 Media Independent Interface (MII) The MII handles the data transfer between the W3100A and the Physical Layer Device. The MII is composed of TX_CLK, TXE, and TXD[0:3] signals for sending data and RX_CLK, RXDV, RXD[0:3], and COL signals for receiving data. When sending data from the W3100A, TXE and TXD[0:3] are output in synchronization with the falling edges of TX_CLK input from the Physical Layer Device because Physical Layer Devices generally recognize the rising edges of TX_CLK. When receiving data, in general, the Physical Layer Devices output RXDV, RXD[0:3], and COL signals in synchronization with the falling edges of RX_CLK, so the W3100A recognizes the signals at the rising edges of RX_CLK. There are serial MII that use 1-bit data signals and nibble MII that use 4-bit data signals. 5.2.1 serial MII This mode is the I/F for 10Mbps Physical Layer Devices, and is composed of 1-bit TXD and RXD. TX_CLK and RX_CLK use a 10MHz cycle. When linking the W3100A with the Physical Layer Device in this mode, RXD and TXD of the Physical Layer Device must be connected to RXD[0] and TXD[0] of the W3100A. oGpGjG~GO~pSGpUPG [_ G 5.2.2 nibble MII This mode is the I/F for 10/100Mbps Physical Layer Devices, and is composed of 4-bit TXD[0:3] and RXD[0:3]. TX_CLK and RX_CLK use a 2.5MHz cycle at 10Mbps and 25MHz at 100Mbps. When linking the W3100A with the Physical Layer Device in this mode, RXD[0:3] and TXD[0:3] of the Physical Layer Device must be connected to RXD[0:3] and TXD[0:3] of the W3100A. The W3100A supports both the serial mode and the nibble mode. G 5.2.3 MII Frame Format TXEN = 0 Start IDLE PREAMBLE of Frame Delimiter PREAMBLE 62B SFD 2B DATA1 DATA2 DATA N-1 DATA N DATA Nibbles IDLE TXEN = 1 TXEN = 0 PREAMBLE SFD DATA IDLE 1 0 1 0 ... ... 62 bits long 11 Between 64 - 1518 data bytes TXEN = 0 5.3.4 Nibble MII Order MAC's SERIAL BIT STREAM LSB FIRST NIBBLE NIBBLE TXD0/RXD0 D0 D1 D2 D3 D4 D5 D6 D7 MSB SECOND TXD1/RXD1 TXD2/RXD2 TXD3/RXD3 G oGpGjG~GO~pSGpUPG [ G Timing Diagrams 1. Clocked mode(CLOCK = 25MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G hG voG jzG jv oG ykG vs s kGG oTG kG}G vl voG TIMING WAVEFORM OF Register/Memory WRITE CYCLE G G G G G G G G G G G G G G G (Note: Valid period of Address signal should be larger than or equal to assertion period of CS signal.) G kGG k~ koG ~yG ~w jzG hG j~ kG} oGpGjG~GO~pSGpUPG \W G AC Characteristics Direct Mode Symbol Chip select to output Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Write pulse width Write Data to write time overlap Data hold from write time G Indirect Mode Speed Min Max Units ns ns 54 54 6 6 ns ns ns ns ns ns ns ns ns tCO tOE tLZ tOLZ tHZ tOHZ tOH tCW tWP tDW tDH 73 73 13 13 0 56 56 24 7 Symbol Chip select to output Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Write pulse width Write Data to write time overlap Data hold from write time (Note: Above data is based on simulation.) Speed Min Max Units ns ns 54 54 6 6 ns ns ns ns ns ns ns ns ns tCO tOE tLZ tOLZ tHZ tOHZ tOH tCW tWP tDW tDH 81 81 13 13 0 56 56 24 7 oGpGjG~GO~pSGpUPG \X G 2. External clocked mode(EXT_CLK = 50MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G hG voG jzG jv oG ykG vs s kGG oTG kG}G vl voG TIMING WAVEFORM OF Register/Memory WRITE CYCLE G G G G G G G G G G G G G G G (Note: Valid period of Address signal should be larger than or equal to assertion period of CS signal.) kGG k~ koG ~yG ~w jzG hG j~ kG} oGpGjG~GO~pSGpUPG \Y G AC Characteristics Direct Mode Symbol Chip select to output Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Write pulse width Write Data to write time overlap Data hold from write time G Indirect Mode Speed Min Max Units ns ns 34 34 6 6 ns ns ns ns ns ns ns ns ns tCO tOE tLZ tOLZ tHZ tOHZ tOH tCW tWP tDW tDH 53 53 13 13 0 36 36 24 7 Symbol Chip select to output Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Write pulse width Write Data to write time overlap Data hold from write time (Note: Above data is based on simulation.) Speed Min Max Units ns ns 34 34 6 6 ns ns ns ns ns ns ns ns ns tCO tOE tLZ tOLZ tHZ tOHZ tOH tCW tWP tDW tDH 61 61 13 13 0 36 36 24 7 oGpGjG~GO~pSGpUPG \Z G 3. Non-clocked mode(CLOCK = 25MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G hG voG jzG jyG ykG vs s kGG oTG kG}G jv oG vl yj voG TIMING WAVEFORM OF Register/Memory WRITE CYCLE / / / hG / / / / / / / / / / / / G (Note: Valid period of Address signal should be larger than or equal to assertion period of CS signal.) G kGG k~ koG ~yG jz~G ~w ~j jzG j~ ~y kG} oGpGjG~GO~pSGpUPG \[ G AC Characteristics Direct Mode Symbol Chip select to output Chip select low to Read low Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Read high to Chip select high Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Address set-up time Chip select low to write low Write high to Chip select high Write Write pulse width Write recovery time Data to write time overlap Data hold from write time G Speed Min Max Units ns ns ns 8 8 ns ns ns 5 5 5 ns ns ns ns ns ns ns ns ns ns ns tCO tCR tOE tLZ tOLZ tRC tHZ tOHZ tOH tCW tAS tCSW tWC tWP tWR tDW tDH 11 5 10 4 4 0 5 0 0 0 5 1 4 5 (Note1: In Non-clocked mode, assertion period of CS signal should enclose assertion period of RD, WR signal. Especially, read signal should be asserted 5ns previously. Note2: In case of Non-clocked mode, high speed working is possible because access time is short. But, you'd better consider MCU setup time to design in order to have bus access time more than enough compared to above data. Note3: Above data is based on simulation.) oGpGjG~GO~pSGpUPG \\ G Indirect Mode Symbol Chip select to output Chip select low to Read low Output enable to valid output Chip select to low-Z output Read Output enable to low-Z output Read high to Chip select high Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip select to end of write Address set-up time Chip select low to write low Write high to Chip select high Write Write pulse width Write recovery time Data to write time overlap Data hold from write time (Note: Above data is based on simulation.) G Speed Min Max Units ns ns ns 8 8 ns ns ns 5 5 5 ns ns ns ns ns ns ns ns ns ns ns tCO tCR tOE tLZ tOLZ tRC tHZ tOHZ tOH tCW tAS tCSW tWC tWP tWR tDW tDH 18 5 18 4 4 0 13 0 0 0 13 1 12 5 oGpGjG~GO~pSGpUPG \] G 4. I2C mode(CLOCK = 25MHz) I C BUS START/STOP BITS TIMINGG 2 zjsG zhzG zhoG zkhG z{hy{G z{vwG zvz zvoG I C BUS DATA TIMING jo zjsG y{G zkhG v} zkhG ko js m{ 2 kz oGpGjG~GO~pSGpUPG \^ G AC Characteristics Symbol START condition setup time START condition hold time STOP condition setup time STOP condition hold time Clock Frequency, SCL SCL high time SCL low time BUS DATA TIMING SDA, SCL rise time SDA, SCL fall time Data input hold time Data input setup time Output valid from clock (Note: Above data is based on simulation.) Speed Min Max Units ns ns ns ns 1 MHz ns ns ns ns START / STOP BITS TIMING tSAS tSAH tSOS tSOH fSCL tCH tCL tRT tFT tDH tDS tOV 40 40 40 40 200 300 0 0 285 ns ns ns G oGpGjG~GO~pSGpUPG \_ G 5. Media Independent Interface (MII) MII Tx TIMING G {jsr {lu {k { G { G AC Characteristics Parameter Tco Tdcs Tco Tdcs G G Description TX_CLK to TXD, TX_EN TXD, TX_EN setup time to TX_CLK TX_CLK to TXD, TX_EN TXD, TX_EN setup time to TX_CLK Notes 10Mbps 10Mbps 100Mbps 100Mbps Min 202 195 22 15 Typ - Max 205 198 25 18 Units ns ns ns ns oGpGjG~GO~pSGpUPG \ G G MII Rx TIMING yjsr ylu yk G { { G G AC Characteristics Parameter Tdcs Tcdh Tdcs Tcdh Description Valid Data to RX_CLK (setup) RX_CLK to Valid Data (hold) Valid Data to RX_CLK (setup) RX_CLK to Valid Data (hold) Notes 10Mbps 10Mbps 100Mbps 100Mbps Min 5 5 5 5 Typ - Max - Units ns ns ns ns oGpGjG~GO~pSGpUPG ]W G Package Description G Figure 1: W3100A LQFP Package Specifications G G G oGpGjG~GO~pSGpUPG ]X G Appendix A. Electrical Specifications ABSOLUTE MAXIMUM RATINGS Symbol Parameter Rating Unit VDD VIN IIN TSTG DC supply voltage DC input voltage DC input current Storage temperature -0.3 to 3.8 -0.3 to 5.5(5V-tolerant) 10 V V mA C -40 to 125 *COMMENT: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. RECOMMENDED OPERATING CONDITIONS Parameter Rating Unit C C Commercial temperature range Industrial temperature range 0 to 70 -10 to 70 D.C. OPERATING CHARACTERISTICS VDD = 3.3 0.3V, VEXT = 5 0.25V Symbol Parameter Condition Min Typ Max Unit VIH VIL High level input voltage Low level input voltage VIN=VDD 2.0 0.8 -10 10 -10 -60 2.4 0.4 -10 10 55 -55 bi4 4 -30 30 10 60 10 -10 V V A IIH High level input current VIN=VDD (External Pull-down) VIN=VSS IIL Low level input current VIN=VSS (External Pull-up) A VOH VOL IOZ High level output voltage Low level output voltage Tri-state output leakage current Output short circuit current Input capacitance Note1 IOH=-4mA IOL=4mA VOUT=VSS or VEXT V V A IOS VDD=3.6V, VO=VDD VDD=3.6V,VO=VSS Any input and mA CIN COUT directional buffers Note1 pF pF Output capacitance Any output buffer *Notes: This value excludes package parasitics. oGpGjG~GO~pSGpUPG ]Y G POWER DISSIPATION Symbol Condition Power Consumption Unit Minimum P10BASE Typical Maximum Minimum P100BASE Typical Maximum G 5 9 11 10 30 35 mA oGpGjG~GO~pSGpUPG ]Z |
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